Real-time rate distortion-optimized image compression with region of interest on the ARM architecture for underwater robotics applications

Abstract

This paper proposes the use of a real-time progressive image compression and region of interest algorithm for the ARM processor architecture. This algorithm is used for the design of an underwater image sensor for an autonomous underwater vehicle for intervention, under a highly constrained available bandwidth scenario, allowing for a more agile data exchange between the vehicle and a human operator supervising the underwater intervention. For high compression ratios (smaller output size), execution time is dominated by the transformation algorithm, which plays a progressively smaller role as the compression ratio gets smaller (larger output size). A novel progressive rate distortion-optimized image compression algorithm based on the discrete wavelet transform (DWT) is presented, with special emphasis on a novel minimal time parallel DWT algorithm, which allows full memory bandwidth saturation using only a few cores of a modern multicore embedded processor. The paper focuses in a novel efficient inplace, multithreaded, and cache-friendly parallel 2-D wavelet transform algorithm, based on the lifting transform using the ARM Architecture. In order to maximize the cache utilization and consequently minimize the memory bus bandwidth use, the threads compete to work on a small memory area, maximizing the chances of finding the data in the cache. Their synchronization is done with very low overhead, without the use of any locks and relying solely on the basic compare-and-swap atomic primitive. An implementation in C programming language with and without the use of vector instructions (single instruction multiple data) is provided for both, single (serial) and multi-(parallel) threaded single-loop DWT implementations, as well as serial and parallel naive implementations using linear (row order) and strided (column order) memory access patterns for comparison. Results show a significant improvement over the single-threaded optimized implementation and a much greater improvement over both, the single- and multi-threaded naive implementations, reaching minimal running time depending on the memory access pattern, the number of processor cores, and the available memory bus bandwidth, i.e., it becomes memory bound using the minimum number of memory accesses. Due to memory saturation, the inplace 2-D DWT transform can be executed in the same time as a 1-D DWT transform or as an inplace memory block copy.