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dc.contributor.authorRodríguez Sánchez, Rafael
dc.contributor.authorQuintana Ortí, Enrique S.
dc.date.accessioned2017-05-29T13:47:11Z
dc.date.available2017-05-29T13:47:11Z
dc.date.issued2016-05
dc.identifier.citationRODRÍGUEZ-SÁNCHEZ, Rafael; QUINTANA-ORTÍ, Enrique S. Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors. Journal of Real-Time Image Processing, 2016, p. 1-14.ca_CA
dc.identifier.urihttp://hdl.handle.net/10234/167673
dc.description.abstractLow-power asymmetric multicore processors (AMPs) have attracted considerable attention due to their appealing performance/power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload. The recent HEVC standard, which offers several high-level parallelization strategies, is an important application that can benefit from an implementation tailored for the low-power AMPs present in many current mobile or handheld devices. In this scenario, we present an architecture-aware implementation of an HEVC decoder that embeds a criticality-aware scheduling strategy tuned for a Samsung Exynos 5422 System-on-Chip furnished with an ARM big.LITTLE AMP. The performance and energy efficiency of our solution are further enhanced by exploiting the NEON vector engine available in the ARM big.LITTLE architecture. Our experimental results expose a 1080p real-time HEVC decoding at 24 frames/s and a reduction of energy consumption over 20 %.ca_CA
dc.description.sponsorShipThis work was supported by Project CICYT TIN2014-53495-R of MINECO and FEDER.ca_CA
dc.format.extent17 p.ca_CA
dc.format.mimetypeapplication/pdfca_CA
dc.language.isoengca_CA
dc.publisherSpringer Verlagca_CA
dc.relation.isPartOfJournal of Real-Time Image Processing March 2017, Volume 13, Issue 1ca_CA
dc.rights© Springer-Verlag Berlin Heidelberg 2016ca_CA
dc.subjectHEVCca_CA
dc.subjectasymmetric multicore processorsca_CA
dc.subjectschedulingca_CA
dc.subjectvector intrinsicsca_CA
dc.subjectreal-time decodingca_CA
dc.subjectenergy efficiencyca_CA
dc.titleArquitecture-aware optimization of an hevc decoder on asymmetric multicore processorsca_CA
dc.typeinfo:eu-repo/semantics/articleca_CA
dc.identifier.doihttp://dx.doi.org/10.1007/s11554-016-0606-y
dc.rights.accessRightsinfo:eu-repo/semantics/restrictedAccessca_CA
dc.relation.publisherVersionhttps://link.springer.com/article/10.1007/s11554-016-0606-yca_CA


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