Evaluating the computational performance of the Xilinx Ultrascale plus EG Heterogeneous MPSoC
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comunitat-uji-handle2:10234/7036
comunitat-uji-handle3:10234/8620
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INVESTIGACIONMetadata
Title
Evaluating the computational performance of the Xilinx Ultrascale plus EG Heterogeneous MPSoCDate
2020-06-06Publisher
SpringerBibliographic citation
Belloch, J.A., León, G., Badía, J.M. et al. Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC. J Supercomput (2020). https://doi.org/10.1007/s11227-020-03342-7Type
info:eu-repo/semantics/articlePublisher version
https://link.springer.com/article/10.1007/s11227-020-03342-7Version
info:eu-repo/semantics/submittedVersionAbstract
The emergent technology of Multi-Processor System-on-Chip (MPSoC), which combines heterogeneous computing with the high performance of Field Programmable Gate Arrays (FPGAs) is a very interesting platform for a huge ... [+]
The emergent technology of Multi-Processor System-on-Chip (MPSoC), which combines heterogeneous computing with the high performance of Field Programmable Gate Arrays (FPGAs) is a very interesting platform for a huge number of applications ranging from medical imaging and augmented reality to high-performance computing in space. In this paper, we focus on the Xilinx Zynq UltraScale+ EG Heterogeneous MPSoC, which is composed of four different processing elements (PE): a dual-core Cortex-R5, a quad-core ARM Cortex-A53, a graphics processing unit (GPU) and a high end FPGA. Proper use of the heterogeneity and the different levels of parallelism of this platform becomes a challenging task. This paper evaluates this platform and each of its PEs to carry out fundamental operations in terms of computational performance. To this end, we evaluate image-based applications and a matrix multiplication kernel. On former, the image-based applications leverage the heterogeneity of the MPSoc and strategically distributes its tasks among both kinds of CPU cores and the FPGA. On the latter, we analyze separately each PE using different matrix multiplication benchmarks in order to assess and compare their performance in terms of MFlops. This kind of operations are being carried out for example in a large number of space-related applications where the MPSoCs are currently gaining momentum. Results stand out the fact that different PEs can collaborate efficiently with the aim of accelerating the computational-demanding tasks of an application. Another important aspect to highlight is that leveraging the parallel OpenBLAS library we achieve up to 12 GFlops with the four Cortex-A53 cores of the platform, which is a considerable performance for this kind of devices. [-]
Investigation project
Spanish Government through TIN2017-82972-R, ESP2015-68245-C4-1-P, the Valencian Regional Government through PROMETEO/2029/109 and the Universitat Jaume I through UJI-B2019-36Rights
© 2020 Springer Nature Switzerland AG. Part of Springer Nature.
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