Modular Multi-level Converter Hardware-in-the-Loop Simulation on low-cost System-on-Chip devices
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Other documents of the author: Tormo, Daniel; Vidal-Albalate, Ricardo; Idkhajine, L.; Monmasson, Eric; Blasco-Gimenez, Ramon
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Title
Modular Multi-level Converter Hardware-in-the-Loop Simulation on low-cost System-on-Chip devicesAuthor (s)
Date
2018-09-21Publisher
IEEEBibliographic citation
D. Tormo, R. Vidal-Albalate, L. Idkhajine, E. Monmasson and R. Blasco-Gimenez, "Modular Multi-level Converter Hardware-in-the-Loop Simulation on low-cost System-on-Chip devices," IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society, Washington, DC, 2018, pp. 2827-2832, doi: 10.1109/IECON.2018.8591256.Type
info:eu-repo/semantics/conferenceObjectPublisher version
https://ieeexplore.ieee.org/document/8591256Version
info:eu-repo/semantics/acceptedVersionSubject
Abstract
System-on-Chip (SoC) devices combine powerful general purpose processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for Hardware-in-the-Loop (HIL) simulation. One of ... [+]
System-on-Chip (SoC) devices combine powerful general purpose processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for Hardware-in-the-Loop (HIL) simulation. One of the limitations of these devices is that control engineers are not particularly familiarized with FPGA programming, which need extensive expertise in order to code these highly sophisticated algorithms using Hardware Description Languages (HDL). Notwithstanding, there exist High-Level Synthesis (HLS) tools which allow to program these devices using more generic programming languages such as C, C++ and SystemC. This paper evaluates SoC devices to implement a Modular Multi-Level Converter (MMC) model using HLS tools for being implemented in the FPGA fabric in order to perform HIL verification of control algorithms in a single low-cost device. [-]
Description
Comunicació presentada a IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society (October 21-23, 2018 Washington D.C., USA.)
Investigation project
Spanish Ministry of Economy and EU FEDER (Grant DPI2014-53245-R)Rights
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