Revisiting conventional task schedulers to exploit asymmetry in multi-core architectures for dense linear algebra operations
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Show full item recordcomunitat-uji-handle:10234/9
comunitat-uji-handle2:10234/7036
comunitat-uji-handle3:10234/8620
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Title
Revisiting conventional task schedulers to exploit asymmetry in multi-core architectures for dense linear algebra operationsAuthor (s)
Date
2017Publisher
ElsevierISSN
0167-8191Type
info:eu-repo/semantics/articlePublisher version
http://www.sciencedirect.com/science/article/pii/S0167819117300856Version
info:eu-repo/semantics/submittedVersionAbstract
Dealing with asymmetry in the architecture opens a plethora of questions related with
the performance- and energy-efficient scheduling of task-parallel applications. While there
exist early attempts to tackle this ... [+]
Dealing with asymmetry in the architecture opens a plethora of questions related with
the performance- and energy-efficient scheduling of task-parallel applications. While there
exist early attempts to tackle this problem, for example via ad-hoc strategies embedded in
a runtime framework, in this paper we take a different path, which consists in addressing
the asymmetry at the library-level by developing a few asymmetry-aware fundamental
kernels. The appealing consequence is that the architecture heterogeneity remains then
hidden from the task scheduler.
In order to illustrate the advantage of our approach, we employ two well-known matrix
factorizations, key to the solution of dense linear systems of equations. From the perspective
of the architecture, we consider two low-power processors, one of them equipped
with ARM big.LITTLE technology; furthermore, we include in the study a different scenario,
in which the asymmetry arises when the cores of an Intel Xeon server operate at two distinct
frequencies. For the specific domain of dense linear algebra, we show that dealing
with asymmetry at the library-level is not only possible but delivers higher performance
than a naive approach based on an asymmetry-oblivious scheduler. Furthermore, this solution
is also competitive in terms of performance compared with an ad-hoc asymmetryaware
scheduler furnished with sophisticated scheduling techniques. [-]
Is part of
Parallel Computing 68 (2017)Investigation project
TIN 2015-65277-R ; TIN2012-32180 ; TIN2011-23283 ; TIN2014-53495-RRights
0167-8191/© 2017 Elsevier B.V. All rights reserved.
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