Energy Balance between Voltage-Frequency Scaling and Resilience for Linear Algebra Routines on Low-Power Multicore Architectures
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Altres documents de l'autoria: Catalán, Sandra; Herrero Zaragoza, José R.; Quintana-Orti, Enrique S.; Rodríguez Sánchez, Rafael
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INVESTIGACIONMetadades
Títol
Energy Balance between Voltage-Frequency Scaling and Resilience for Linear Algebra Routines on Low-Power Multicore ArchitecturesAutoria
Data de publicació
2017Editor
ElsevierISSN
0167-8191Cita bibliogràfica
S. Catalán et al., Energy balance between voltage-frequency scaling and resilience for linear algebra routines on low-power multicore architectures, Parallel Computing (2017), http://dx.doi.org/10.1016/j.parco.2017.05.004Tipus de document
info:eu-repo/semantics/articleVersió de l'editorial
http://www.sciencedirect.com/science/article/pii/S0167819117300765Versió
info:eu-repo/semantics/submittedVersionParaules clau / Matèries
Resum
Near Threshold Voltage (NTV) computing has been recently proposed as a technique to save energy, at the cost of incurring higher error rates including, among others, Silent Data Corruption (SDC). In this paper, we ... [+]
Near Threshold Voltage (NTV) computing has been recently proposed as a technique to save energy, at the cost of incurring higher error rates including, among others, Silent Data Corruption (SDC). In this paper, we evaluate the energy efficiency of dense linear algebra routines using several low-power multicore processors and we analyze whether the potential energy reduction achieved when scaling the processor to operate at a low voltage compensates the cost of integrating a fault tolerance mechanism that tackles SDC. Our study targets algorithmic-based fault-tolerant versions of the dense matrix-vector and matrix(-matrix) multiplication kernels (gemv and gemm, respectively), using the BLIS framework, as well as an implementation of the LU factorization with partial pivoting built on top of gemm. Furthermore, we tailor the study for a number of representative 32-bit and 64-bit multicore processors from ARM that were specifically designed for energy efficiency. [-]
Publicat a
Parallel Computing 000 (2017)Proyecto de investigación
CICYT TIN2014-53495-R ; TIN2015- 65316-PDrets d'accés
0167-8191/© 2017 Elsevier B.V. All rights reserved.
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info:eu-repo/semantics/openAccess
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