Arquitecture-aware optimization of an hevc decoder on asymmetric multicore processors
comunitat-uji-handle:10234/9
comunitat-uji-handle2:10234/7036
comunitat-uji-handle3:10234/8620
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http://dx.doi.org/10.1007/s11554-016-0606-y |
Metadatos
Título
Arquitecture-aware optimization of an hevc decoder on asymmetric multicore processorsFecha de publicación
2016-05Editor
Springer VerlagCita bibliográfica
RODRÍGUEZ-SÁNCHEZ, Rafael; QUINTANA-ORTÍ, Enrique S. Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors. Journal of Real-Time Image Processing, 2016, p. 1-14.Tipo de documento
info:eu-repo/semantics/articleVersión de la editorial
https://link.springer.com/article/10.1007/s11554-016-0606-yPalabras clave / Materias
Resumen
Low-power asymmetric multicore processors (AMPs) have attracted considerable attention due to their appealing performance/power ratio for energy-constrained environments. However, these processors pose a significant ... [+]
Low-power asymmetric multicore processors (AMPs) have attracted considerable attention due to their appealing performance/power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload. The recent HEVC standard, which offers several high-level parallelization strategies, is an important application that can benefit from an implementation tailored for the low-power AMPs present in many current mobile or handheld devices. In this scenario, we present an architecture-aware implementation of an HEVC decoder that embeds a criticality-aware scheduling strategy tuned for a Samsung Exynos 5422 System-on-Chip furnished with an ARM big.LITTLE AMP. The performance and energy efficiency of our solution are further enhanced by exploiting the NEON vector engine available in the ARM big.LITTLE architecture. Our experimental results expose a 1080p real-time HEVC decoding at 24 frames/s and a reduction of energy consumption over 20 %. [-]
Publicado en
Journal of Real-Time Image Processing March 2017, Volume 13, Issue 1Derechos de acceso
© Springer-Verlag Berlin Heidelberg 2016
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