Embedded Real-Time Simulator for Sensorless Control of Modular Multi-Level Converters
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Otros documentos de la autoría: Tormo, Daniel; Vidal-Albalate, Ricardo; IDKHAJINE, LAHOUCINE; Monmasson, Eric; Blasco-Gimenez, Ramon
Metadatos
Mostrar el registro completo del ítemcomunitat-uji-handle:10234/9
comunitat-uji-handle2:10234/7034
comunitat-uji-handle3:10234/8619
comunitat-uji-handle4:
INVESTIGACIONMetadatos
Título
Embedded Real-Time Simulator for Sensorless Control of Modular Multi-Level ConvertersAutoría
Fecha de publicación
2022-02-25Editor
MDPIISSN
2079-9292Cita bibliográfica
Tormo, D.; Vidal-Albalate, R.; Idkhajine, L.; Monmasson, E.; Blasco-Gimenez, R. Embedded Real-Time Simulator for Sensorless Control of Modular Multi-Level Converters. Electronics 2022, 11, 719.Tipo de documento
info:eu-repo/semantics/articleVersión
info:eu-repo/semantics/publishedVersionPalabras clave / Materias
Resumen
This paper suggests the application of an embedded real-time simulator (eRTS) in the
context of voltage–sensorless control of a modular multilevel power converter (MMC). This eRTS
acts as an observer and ensures ... [+]
This paper suggests the application of an embedded real-time simulator (eRTS) in the
context of voltage–sensorless control of a modular multilevel power converter (MMC). This eRTS
acts as an observer and ensures digital redundancy in the case of any fault occurring among the
capacitor voltage sensors of the MMC submodules. Hence, in such a faulty situation, the MMC
controller switches from the measured voltages to their estimated counterparts. As for the digital
implementation, to ensure a high level of integration of the overall control system, the Xilinx Zynq7020 system-on-chip field programmable gate array (SoC-FPGA) device was used. The controller was
implemented in the hardwired ARM Cortex-A9 processor, with a 100 µs time step. Regarding the
time-sensitive blocks (PWM, eRTS and measurements filtering), a full hardware implementation was
privileged, using the FPGA fabric. The execution time of these blocks was 710 ns with a 100 MHz
system clock, and the synchronization with the analog to digital acquisition chain was made with
a 5 µs time resolution. The whole proof-of-concept system was experimentally tested, including
the time/area evaluation of the implemented designs and the experimental validation of the eRTS
estimations in both healthy and faulty scenarios. [-]
Publicado en
Electronics 2022, 11, 719Derechos de acceso
info:eu-repo/semantics/openAccess
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