Balanced and Compressed Coordinate Layout for the Sparse Matrix-Vector Product on GPUs
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Otros documentos de la autoría: Aliaga Estellés, José Ignacio; Anzt, Hartwig; Quintana-Orti, Enrique S.; Tomás Domínguez, Andrés Enrique; Tsai, Yuhsiang M.
Metadatos
Mostrar el registro completo del ítemcomunitat-uji-handle:10234/9
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comunitat-uji-handle3:10234/146069
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INVESTIGACIONMetadatos
Título
Balanced and Compressed Coordinate Layout for the Sparse Matrix-Vector Product on GPUsAutoría
Fecha de publicación
2021Editor
SpringerISBN
978-3-030-71592-2; 978-3-030-71593-9ISSN
0302-9743Cita bibliográfica
Aliaga, J.I., Anzt, H., Quintana-Ortí, E.S., Tomás, A.E., Tsai, Y.M. (2021). Balanced and Compressed Coordinate Layout for the Sparse Matrix-Vector Product on GPUs. In: , et al. Euro-Par 2020: Parallel Processing Workshops. Euro-Par 2020. Lecture Notes in Computer Science(), vol 12480. Springer, Cham. https://doi.org/10.1007/978-3-030-71593-9_7Tipo de documento
info:eu-repo/semantics/conferenceObjectVersión de la editorial
https://link.springer.com/chapter/10.1007/978-3-030-71593-9_7Versión
info:eu-repo/semantics/submittedVersionPalabras clave / Materias
Resumen
We contribute to the optimization of the sparse matrix-vector product on graphics processing units by introducing a variant of the coordinate sparse matrix layout that compresses the integer representation of the ... [+]
We contribute to the optimization of the sparse matrix-vector product on graphics processing units by introducing a variant of the coordinate sparse matrix layout that compresses the integer representation of the matrix indices. In addition, we employ a look-ahead table to avoid the storage of repeated numerical values in the sparse matrix, yielding a more compact data representation that is easier to maintain in the cache. Our evaluation on the two most recent generations of NVIDIA GPUs, the V100 and the A100 architectures, shows considerable performance improvements over the kernels for the sparse matrix-vector product in cuSPARSE (CUDA 11.0.167). [-]
Publicado en
European Conference on Parallel Processing. Springer, Cham, 2020Entidad financiadora
Ministerio de Ciencia, Innovación y Universidades | Helmholtz Association | Exascale Computing Project | European Commission
Código del proyecto o subvención
MICIU/ICTI2017-2020/TIN2017-82972-R | VH-NG-1241 | 17-SC-20-SC
Proyecto de investigación
info:eu-repo/grantAgreement/EC/H2020/732631Derechos de acceso
© Springer Nature Switzerland AG
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