Load-balancing Sparse Matrix Vector Product Kernels on GPUs
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Other documents of the author: Anzt, Hartwig; Cojean, Terry; Yen-Chen, Chen; Dongarra, Jack; Flegar, Goran; Nayak, Pratik; Tomov, Stanimire; Tsai, Yuhsiang M.; Wang, Weichung
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https://doi.org/10.1145/3380930 |
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Title
Load-balancing Sparse Matrix Vector Product Kernels on GPUsAuthor (s)
Date
2020-03Publisher
Association for Computing Machinery (ACM)ISSN
2329-4949; 2329-4957Bibliographic citation
Hartwig Anzt, Terry Cojean, Chen Yen-Chen, Jack Dongarra, Goran Flegar, Pratik Nayak, Stanimire Tomov, Yuhsiang M. Tsai, and Weichung Wang. 2020. Load-balancing Sparse Matrix Vector Product Kernels on GPUs. ACM Trans. Parallel Comput. 7, 1, Article 2 (March 2020), 26 pages. DOI:https://doi.org/10.1145/3380930Type
info:eu-repo/semantics/articlePublisher version
https://dl.acm.org/doi/abs/10.1145/3380930Version
info:eu-repo/semantics/publishedVersionAbstract
Efficient processing of Irregular Matrices on Single Instruction, Multiple Data (SIMD)-type architectures is a persistent challenge. Resolving it requires innovations in the development of data formats, computational ... [+]
Efficient processing of Irregular Matrices on Single Instruction, Multiple Data (SIMD)-type architectures is a persistent challenge. Resolving it requires innovations in the development of data formats, computational techniques, and implementations that strike a balance between thread divergence, which is inherent for Irregular Matrices, and padding, which alleviates the performance-detrimental thread divergence but introduces artificial overheads. To this end, in this article, we address the challenge of designing high performance sparse matrix-vector product (SpMV) kernels designed for Nvidia Graphics Processing Units (GPUs). We present a compressed sparse row (CSR) format suitable for unbalanced matrices. We also provide a load-balancing kernel for the coordinate (COO) matrix format and extend it to a hybrid algorithm that stores part of the matrix in SIMD-friendly Ellpack format (ELL) format. The ratio between the ELL- and the COO-part is determined using a theoretical analysis of the nonzeros-per-row distribution. For the over 2,800 test matrices available in the Suite Sparse matrix collection, we compare the performance against SpMV kernels provided by NVIDIA's cuSPARSE library and a heavily-tuned sliced ELL (SELL-P) kernel that prevents unnecessary padding by considering the irregular matrices as a combination of matrix blocks stored in ELL format. [-]
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ACM Transactions on Parallel Computing, 2020, vol. 7, no 1Rights
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