Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics
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Otros documentos de la autoría: Chalios, Charalampos; Nikolopoulos, Dimitrios S.; Catalán, Sandra; Quintana-Orti, Enrique S.
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Metadatos
Título
Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metricsAutoría
Fecha de publicación
2016-03Editor
Institution of Engineering and TechnologyCita bibliográfica
CHALIOS, Charalampos, et al. Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics. IET Computers & Digital Techniques, 2016, vol. 10, no 2, p. 85-92.Tipo de documento
info:eu-repo/semantics/articleVersión de la editorial
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7400477Palabras clave / Materias
Resumen
The end of Dennard scaling has promoted low power consumption into a first-order concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their ... [+]
The end of Dennard scaling has promoted low power consumption into a first-order concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, reliability. These limitations would make them unsuitable for HPC systems and datacenters. To demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM's big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the study describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation. [-]
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IET Computers & Digital Techniques Volume 10, Issue 2, 2016Derechos de acceso
© The Institution of Engineering and Technology 2016
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