Optimized Fundamental Signal Processing Operations For Energy Minimization on Heterogeneous Mobile Devices
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Otros documentos de la autoría: BELLOCH, JOSE A.; Badía, José; Igual, Francisco D.; González, Alberto; Quintana-Orti, Enrique S.
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Título
Optimized Fundamental Signal Processing Operations For Energy Minimization on Heterogeneous Mobile DevicesAutoría
Fecha de publicación
2018-05Editor
IEEECita bibliográfica
BELLOCH, Jose A., et al. Optimized Fundamental Signal Processing Operations For Energy Minimization on Heterogeneous Mobile Devices. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65.5: 1614-1627.Tipo de documento
info:eu-repo/semantics/articleVersión de la editorial
https://ieeexplore.ieee.org/abstract/document/8094283Versión
info:eu-repo/semantics/acceptedVersionPalabras clave / Materias
Resumen
Numerous signal processing applications are emerging on both mobile and high-performance
computing systems. These applications are subject to responsiveness constraints for
user interactivity and, at the same time, ... [+]
Numerous signal processing applications are emerging on both mobile and high-performance
computing systems. These applications are subject to responsiveness constraints for
user interactivity and, at the same time, must be optimized for energy efficiency. The
increasingly heterogeneous power-versus-performance profile of modern hardware introduces new opportunities for energy savings as well as challenges. In this line, recent
Systems-On-Chip (SoC) composed of low-power multicore processors, combined with
a small graphics accelerator (or GPU), yield a notable increment of the computational
capacity while partially retaining the appealing low power consumption of embedded
systems. This paper analyzes the potential of these new hardware systems to accelerate applications that involve a large number of floating-point arithmetic operations
mainly in the form of convolutions. To assess the performance, a headphone-based
spatial audio application for mobile devices based on a Samsung Exynos 5422 SoC
has been developed. We discuss different implementations and analyze the trade-offs
between performance and energy efficiency for different scenarios and configurations.
Our experimental results reveal that we can extend the battery lifetime of a device
featuring such an architecture by a 238% by properly configuring and leveraging the
computational resources. [-]
Proyecto de investigación
Spanish Ministerio de Economía y Competitividad (TIN2014-53495- R and TEC2015-67387-C4-1-R) ; University Jaume I (UJI-B2016-20, together with the project PROMETEOII/2014/003) ; Dr. Jose A. Belloch is supported by GVA postdoctoral contract APOSTD/2016/069.Derechos de acceso
© 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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