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Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics
dc.contributor.author | Chalios, Charalampos | |
dc.contributor.author | Nikolopoulos, Dimitrios S. | |
dc.contributor.author | Catalán, Sandra | |
dc.contributor.author | Quintana-Orti, Enrique S. | |
dc.date.accessioned | 2016-07-15T09:02:00Z | |
dc.date.available | 2016-07-15T09:02:00Z | |
dc.date.issued | 2016-03 | |
dc.identifier.citation | CHALIOS, Charalampos, et al. Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics. IET Computers & Digital Techniques, 2016, vol. 10, no 2, p. 85-92. | ca_CA |
dc.identifier.uri | http://hdl.handle.net/10234/161718 | |
dc.description.abstract | The end of Dennard scaling has promoted low power consumption into a first-order concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, reliability. These limitations would make them unsuitable for HPC systems and datacenters. To demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM's big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the study describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation. | ca_CA |
dc.description.sponsorShip | We thank F. D. Igual, from Universidad Complutense de Madrid, for his help with the Odroid board. Sandra Catalán and Enrique S. Quintana-Ortí were supported by projects TIN2011-23283 and TIN2014-53495-R of the MINECO and FEDER, and the EU project FP7 318793 ‘ EXA2GREEN ’ . This work was partially conducted while this author was visiting Queen ’ s University of Belfast. This research has also been supported in part by the European Commission under grant agreements FP7-323872 (ScoRPiO), FP6-610509 (NanoStreams) and by the UK Engineering and Physical Sciences Research Council under grant agreements EP/L000055/1 (ALEA), EP/L004232/1 (ENPOWER) and EP/K017594/1 (GEMSCLAIM) Invited paper from EEHCO HIPEAC. | ca_CA |
dc.format.extent | 7 p. | ca_CA |
dc.format.mimetype | application/pdf | ca_CA |
dc.language.iso | eng | ca_CA |
dc.publisher | Institution of Engineering and Technology | ca_CA |
dc.relation.isPartOf | IET Computers & Digital Techniques Volume 10, Issue 2, 2016 | ca_CA |
dc.rights | © The Institution of Engineering and Technology 2016 | ca_CA |
dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | * |
dc.subject | fault tolerant computing | ca_CA |
dc.subject | integrated circuit reliability | ca_CA |
dc.subject | multiprocessing systems | ca_CA |
dc.subject | system-on-chip | ca_CA |
dc.title | Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics | ca_CA |
dc.type | info:eu-repo/semantics/article | ca_CA |
dc.identifier.doi | http://dx.doi.org/10.1049/iet-cdt.2015.0056 | |
dc.rights.accessRights | info:eu-repo/semantics/restrictedAccess | ca_CA |
dc.relation.publisherVersion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7400477 | ca_CA |
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