Tuning stationary iterative solvers for fault resilience
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TitleTuning stationary iterative solvers for fault resilience
PublisherACM. Association for Computing Machinery
As the transistor’s feature size decreases following Moore’s Law, hardware will become more prone to permanent, intermittent, and transient errors, increasing the number of failures experienced by applications, and ... [+]
As the transistor’s feature size decreases following Moore’s Law, hardware will become more prone to permanent, intermittent, and transient errors, increasing the number of failures experienced by applications, and diminishing the confidence of users. As a result, resilience is considered the most difficult under addressed issue faced by the High Performance Computing community. In this paper, we address the design of error resilient iterative solvers for sparse linear systems. Contrary to most previous ap- proaches, based on Krylov subspace methods, for this purpose we analyze stationary component-wise relaxation. Concretely, starting from a plain implementation of the Jacobi iteration, we design a low-cost component-wise technique that elegantly handles bit-flips, turning the initial synchronized solver into an asynchronous itera- tion. Our experimental study employs sparse incomplete factoriza- tions from several practical applications to expose the convergence delay incurred by the fault-tolerant implementation. [-]
Bibliographic citationAnzt, H., Dongarra, J., & Quintana-Ortí, E. S. (2015, November). Tuning stationary iterative solvers for fault resilience. In Proceedings of the 6th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (p. 1). ACM.
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